1. Field of the Invention
The present invention generally relates to integrated circuit (IC) structures and, more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips.
2. Description of the Prior Art
Fuses are used in integrated circuits (ICs) to disconnect defective regions of a chip, thereby making the chip usable. For example, redundancy in integrated circuit memories is part of current wafer and chip manufacturing strategy to improve yield. The practice is to blow fuses which allow extra memory cells to be used in place of cells that are non-functional. In addition, fuses are used, for example, in programmable logic arrays (PLAS) and similar structures to form semi-custom circuits.
Antifuses are devices that have a lower resistance after programming than initially. Antifuses, like fuses, are used both in redundant IC structures and to form semi-custom circuits. An antifuse using junction breakdown in a bipolar transistor has been described by C. M. Hsieh and H. R. Wilson in "Electrically Programmable Transistor Pipes", IBM Technical Disclosure Bulletin, vol. 24, No. 7A, pp. 3478 and 3479 (1981).
U.S. Pat. No. 5,019,878 to Yang et al. discloses a programmable interconnect using a silicided MOS transistor. The transistor is formed at a face of a semiconductor layer and includes a diffused drain region and a source region that are spaced apart by a channel region. The drain region has a surface with a silicided layer. The application of a programming voltage in the range of ten to fifteen volts from the drain region to the source region forms a melt filament across the channel region. Programming is controlled by applying or not applying a gate voltage over the channel region.
The Yang et al. programmable interconnect is only suitable for field effect transistor (FET) structures because it is itself an FET device requiring the number and type of processing steps of FET structures. Moreover, it has a disadvantage of requiring a relative high program voltage (e.g., ten to fifteen volts) which, in a high density IC device, risks localized damage to other structures in the region.
K.-Y. Fu and R. E. Pyle, in "On the Failure Mechanisms of Titanium Nitride/Titanium Silicide Barrier Contacts under High Current Stress", IEEE Transactions on Electron Devices, vol. 35, no. 12, pp. 2151-2159 (1988), have described a failure mechanism caused by electrically stressing a P-N junction contacted by Al/TiN/TiSi.sub.2 metallurgy. At high current densities, joule heating occurs in the Si substrate, which causes the Al to penetrate the TiN and TiSi.sub.2 layers and spike the junction. However, there is no recognition by the authors that this phenomenon could be used in a positive way.
What is needed is an antifuse of simple construction having application to both FET and bipolar structures. The antifuse should also be programmable using low voltages to minimize the possibility of thermal damage to other structures in the region of the antifuse.